Apply For Senior Design Verification Engineer

• InSemi Technologies
• Office Location
• Full Time

Experience: 5 - 5 years required

Pay:

Salary Information not included

Type: Full Time

Location: Hyderabad

Skills: SOCIP verification, System Verilog coding, OVMUVMmethodology, APBAHBAXIPCIeDDR protocol, Test bench development, Gate Level simulationdebug