Senior Design Verification Engineer InSemi Technologies
InSemi Technologies
Office Location
Full Time
Experience: 5 - 5 years required
Pay:
Salary Information not included
Type: Full Time
Location: Hyderabad
Skills: SOCIP verification, System Verilog coding, OVMUVMmethodology, APBAHBAXIPCIeDDR protocol, Test bench development, Gate Level simulationdebug
About InSemi Technologies
Job Description
As a Senior Design Verification Engineer with 5+ years of experience in Bangalore & Hyderabad, your key responsibilities will include: - Demonstrating expertise in SOC/IP verification and System Verilog Coding. - Utilizing experience in OVM/UVM/methodology for verification processes. - Working in environments involving APB/AHB/AXI/PCIe/DDR protocols. - Developing Test Benches for verification purposes. - Having a good understanding of Gate Level simulation and debugging techniques.,