Apply For RTL Integration (Frontend) Engineer

• EdgeCortix
• Office Location
• Full Time

Experience: 4 - 4 years required

Pay:

Salary Information not included

Type: Full Time

Location: Hyderabad

Skills: Verilog, Ruby, Perl, Python, Makefile, RTL design, synthesis, static timing analysis, Physical Synthesis, AXI, DDR, timing analysis, Power analysis, scripting languages, CC, Tcl, Netlist Power Analysis, Gate level netlists, Physical design flows, Verification infrastructure, ECO Flows, Elab checks, Integration flow automation, Design Constraints, Constraints Analysis, Chisel based environments, PCIeUCIe, NIC, RISC V integration, FPGA integration, Formal equivalence, Cadence tool chain, CPUMemoryBus Integration