EdgeCortix
Employees - 100+, Positions - 1+, Salary - 0 - 0 , Industry Type - IT - Software
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RTL Integration (Frontend) Engineer
EdgeCortix
Office Location
Full Time
- Verilog
- Ruby
- Perl
- Python
- Makefile
- RTL design
- synthesis
- static timing analysis
- Physical Synthesis
- AXI
- DDR
- timing analysis
- Power analysis
- scripting languages
- CC
- Tcl
- Netlist Power Analysis
- Gate level netlists
- Physical design flows
- Verification infrastructure
- ECO Flows
- Elab checks
- Integration flow automation
- Design Constraints
- Constraints Analysis
- Chisel based environments
- PCIeUCIe
- NIC
- RISC V integration
- FPGA integration
- Formal equivalence
- Cadence tool chain
- CPUMemoryBus Integration