Apply For Junior RTL Design Engineer AI Networking

• Auradine
• Office Location
• Full Time

Experience: 3 - 3 years required

Pay:

Salary Information not included

Type: Full Time

Location: All India

Skills: Logic design, timing closure, CPU, gpu, Coding, Debugging, power, synthesis, UVM, Python, Perl, RTL entry, SoC IPs, uArch, digital timing analysis, placenroute, verification principles, testbenches, coverage, instruction set definition, hardwaresoftware partition, on chip cachesmemory, Integer arithmetic, floatingpoint arithmetic, ALU operations, deeply pipelined designs, coherent subsystem design, bus interface, memory ordering models