Auradine
Employees - 100+, Positions - 2+, Salary - 0 - 0 , Industry Type - IT - Software
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Lead Design Verification AI Networking
Auradine
Office Location
Full Time
- UVM
- Formal Verification
- SVTB
- AI Computing
- Networking Interconnects
- Automating Design
- postsilicon validation
- APBAHBAXI Protocols
Salary Information not included
Junior RTL design engineer AI Networking
- Auradine
- Office Location
- Full Time
- Logic design
- timing closure
- CPU
- gpu
- Coding
- Debugging
- power
- synthesis
- UVM
- Python
- Perl
- RTL entry
- SoC IPs
- uArch
- digital timing analysis
- placenroute
- verification principles
- testbenches
- coverage
- instruction set definition
- hardwaresoftware partition
- on chip cachesmemory
- Integer arithmetic
- floatingpoint arithmetic
- ALU operations
- deeply pipelined designs
- coherent subsystem design
- bus interface
- memory ordering models