Apply For FPGA Design Engineer

• Berylline Labs Pvt. Ltd.
• Office Location
• Full Time

Experience: 3 - 3 years required

Pay:

Salary Information not included

Type: Full Time

Location: West Bengal

Skills: VHDL, Verilog, Python, Embedded systems, CC, Digital Readout System Designs, ADCDAC Interfacing, High Speed RF Design, AIML Implementation