FPGA Design Engineer Berylline Labs Pvt. Ltd.
Berylline Labs Pvt. Ltd.
Office Location
Full Time
Experience: 3 - 3 years required
Pay:
Salary Information not included
Type: Full Time
Location: West Bengal
Skills: VHDL, Verilog, Python, Embedded systems, CC, Digital Readout System Designs, ADCDAC Interfacing, High Speed RF Design, AIML Implementation
About Berylline Labs Pvt. Ltd.
Job Description
This requirement is for design and development for candidates with experience and working knowledge of latest AMD/Xilinx FPGAs/SoC/Versal/Alveo/RFSoC devices Responsibilities Candidate will be responsible for firmware coding, hardware implementation using VHDL/Verilog/Python/C/C++. Candidate will be responsible for embedded system design, digital readout system designs, ADC/DAC interfacing, High Speed RF design and AI/ML implementation on FPGA platform development. Qualifications BTech / MTech in Electronics / VLSI / Embedded Systems / Computer Science Minimum 3+ experience in FPGA design and development is mandatory. Only core experience will be considered. Freshers will not be considered. Practical Exposure to FPGA design is mandatory Must have at least one strong skill out of the ones listed under "responsibilities" Must be self driven with strong analytical skills and must be a quick learner Must have good communication skills Must be hard working and focused,