Apply For ASIC Design Engineer (Lead/Senior/Junior RTL Design)

• PerfectVIPs
• Office Location
• Full Time

Experience: 2 - 2 years required

Pay:

Salary Information not included

Type: Full Time

Location: All India

Skills: Verilog, synthesis, STA, CDC, AXI, AHB, SAS, DDR, PCIe, OTN, I2C, SPI, Perl, LEC, EDA, RTLlevel design, FlashMemory