ASIC Design Engineer (Lead/Senior/Junior RTL Design) PerfectVIPs
PerfectVIPs
Office Location
Full Time
Experience: 2 - 2 years required
Pay:
Salary Information not included
Type: Full Time
Location: All India
Skills: Verilog, synthesis, STA, CDC, AXI, AHB, SAS, DDR, PCIe, OTN, I2C, SPI, Perl, LEC, EDA, RTLlevel design, FlashMemory
About PerfectVIPs
Job Description
ASIC Design Engineer (Lead/Senior/Junior RTL Design) Job# VE903 Roles & Responsibilities Define micro architecture from datasheet or requirements document Perform RTL-level design, Synthesis, STA, CDC and Lint for any digital logic Perform module-level verification and lint checking Interact with verification engineers for test plan review, coverage debug Technical Skills Required B.Tech/M.Tech in Electronics/VLSI Engineering with experience of 3-5 years in ASIC Design Strong hands-on experience with Verilog RTL-level design, Synthesis, STA, CDC and Lint Should be able to work independently once the design requirements are specified Knowledge of standard interfaces viz., AXI, AHB, SAS, DDR, PCIe, Flash-Memory, OTN, I2C/SPI is a plus Knowledge of Perl, and EDA tools for LEC, Synthesis is a plus Must have good spoken and written communication skills Collaborate well in a team Lead will manage a team of engineers to perform the above tasks. Experience 2 to 12 Years & above Education BE/ ME/ B.Tech/ M.Tech/ MS Location Bengaluru Ahmedabad Bhubaneswar Noida Hyderabad Pune Onsite in India San Jose, USA,