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Ambit Semiconductors
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Full Time
Experience: 5 - 5 years required
Pay:
Salary Information not included
Type: Full Time
Location: Hyderabad
Skills: RTL Coding, Verilog, SystemVerilog, synthesis, Equivalence Checking, Design Specifications, Design Verification, Floorplan, Timing Constraints, Mixed signal concepts, ClockDomain Crossing CDC Analysis, AreaPower optimizations, linting, Power intent, Static Timing Analysis STA, Microarchitecture diagrams, Power Reduction, Timing Convergence
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