Apply For ASIC RTL Design Architect

• Sykatiya Technologies Pvt Ltd
• Office Location
• Full Time

Experience: 10 - 10 years required

Pay:

Salary Information not included

Type: Full Time

Location: Karnataka

Skills: RTL design, Verilog, SystemVerilog, Lint, CDC, Spyglass, PCIe, DDR, Serdes, EDA tools, Python, Perl, ASIC, SoC microarchitecture, UVMbased verification, Tcl