STA Engineer!None! Sventl Asia Pacific
Sventl Asia Pacific
Office Location
Full Time
Experience: 4 - 4 years required
Pay:
Salary Information not included
Type: Full Time
Location: Karnataka
Skills: static timing analysis, STA, RTL, timing analysis, Scripting, Perl, Python, Synopsys NanoTime, PVT corners, Timing Constraints, timing ECOs, Tcl, digital design flow
About Sventl Asia Pacific
Job Description
About the Role: We are looking for a Static Timing Analysis (STA) Engineer with hands-on experience using Synopsys NanoTime or similar tools to join our growing team in Singapore. You will be part of a high-performance SoC design team responsible for timing signoff and analysis of cutting-edge IPs and chips in advanced process nodes (e.g., 5nm, 3nm). Responsibilities: Perform full-chip and block-level Static Timing Analysis using NanoTime Collaborate with physical design and RTL teams to meet timing closure Apply timing constraints and perform timing ECOs as required Run timing analysis across multiple PVT corners and modes Support design sign-off activities (STA, SI, cross-talk, OCV, etc.) Optimize timing performance while balancing power and area trade-offs Requirements: Bachelor's or Master's degree in Electrical/Electronics Engineering or related 4+ years of experience in STA, with NanoTime or PrimeTime Strong knowledge of STA concepts, PVT corners, constraints (SDC), and timing reports Familiarity with advanced process nodes (e.g., 7nm, 5nm or below) Scripting skills in TCL, Perl, or Python for automation Good understanding of digital design flow and timing closure,