Senior / Lead RTL Design Engineer Sykatiya Technologies Pvt Ltd

About Sykatiya Technologies Pvt Ltd

Job Description

You will be responsible for running Logic/Physical Synthesis using advanced optimization techniques to generate an optimized Gate Level Netlist for Timing, Area, and Power. In addition, you will debug timing, area, and congestion issues and collaborate with RTL & Physical designers to resolve them effectively. Your role will involve performing Power Estimation at both RTL and Gate Level, identifying power reduction opportunities, and executing Formal Verification checks between RTL and Gate level netlist. You will be responsible for debugging aborts, inconclusive results, and Logic Equivalency failures. In this position, you will also be required to conduct RTL Lint, collaborate with Designers to create waivers, and perform RTL DFT Analysis to enhance DFT coverage for Stuck-at faults. Additionally, you will develop Timing Constraints for RTL-Synthesis and PrimeTime-STA for blocks and top-level, including SOC. Analyzing inter-block timing and proposing IO budgets for various partition blocks will also be part of your responsibilities. Furthermore, you will play a key role in developing Automation scripts and Methodology for all Front-End tools, such as Lint, CDC, RDC, Synthesis, STA, and Power. Your collaboration with Design Engineers, DV Engineers, and Emulation Engineers to support handoff tasks will be crucial. You will also interact with Physical Design Engineers, providing them with timing and congestion feedback as needed.,