RTL ASIC Engineer (All Levels) Blueberry Semiconductors
Blueberry Semiconductors
Office Location
Full Time
Experience: 1 - 1 years required
Pay:
Salary Information not included
Type: Full Time
Location: Karnataka
Skills: RTL design, Verilog, System Verilog, ASIC design, timing analysis, DFT, Implementation, UPF, CDC, RDC, Lint, Clocking, Power management, Interconnect, Safety, Security, Architecture, Low power signoff, DEBUG
About Blueberry Semiconductors
Job Description
You should be an ASIC designer with a minimum of 1-15 years of experience in RTL design using Verilog/System Verilog. Your expertise should cover all aspects of the RTL design flow, including Specification/Microarchitecture definition, design and verification, Timing Analysis, DFT, and Implementation. You should also have experience in Integration, RTL signoff tools, UPF/Low power signoff, CDC/RDC, and Lint. Your domain knowledge should be strong in Clocking, System modes, Power management, debug, interconnect, safety, security, and other architectures. As a highly motivated individual, you should be a self-starter with excellent interpersonal skills and the ability to work effectively in a team. Strong communication, critical thinking, and problem-solving skills are essential for this role. Preferred education for this position is any degree.,