RTL ASIC Design Engineer/ Lead/ Manager Tessolve
Tessolve
Office Location
Full Time
Experience: 3 - 3 years required
Pay:
Salary Information not included
Type: Full Time
Location: Karnataka
Skills: Microarchitecture, Verilog Coding, I2C, SPI, UART, APB, AHB, AXI, Lint, CDC, RTL Coding, Team Leadership, RTL ASIC front end design, MAS development, Development of module, Medium complexity protocol, AMBA bus protocols, Quality check flows, MicroArchitechture, IP design, Subsystem design, soc integration
About Tessolve
Job Description
You will be responsible for RTL ASIC front end design involving Microarchitecture and Verilog coding. This includes MAS development, RTL coding, module development, and feature addition. You should have experience working with medium complexity protocols and be well-versed in slow speed protocols like I2C/SPI/UART. Familiarity with AMBA bus protocols (APB, AHB, AXI) is essential. Additionally, you should have experience in Quality check flows such as Lint/CDC. For candidates with 8+ years of experience, you are expected to have a very strong background in RTL coding. You should have expertise in Micro-Architecture development, owning and delivering a Sub-system or Top level in a SoC project. Experience in IP design, Sub-system design, SoC integration, and successful team leadership are key requirements for this role. If you are interested in this position, please share your updated CV with gayatri.kushe@tessolve.com or connect on 6361542656.,