Functional Verification Engineer(4-8 Years) SpanIdea Systems
SpanIdea Systems
Office Location
Full Time
Experience: 4 - 4 years required
Pay:
Salary Information not included
Type: Full Time
Location: Hyderabad
Skills: System Verilog, UVM
About SpanIdea Systems
Job Description
The ideal candidate must have hands-on experience coding in System Verilog/UVM and developing test benches for block level or IP level verification. Experience working on subsystem or SoC level would be beneficial. As a proactive communicator, you should be able to work independently to self-manage deliverables according to schedules. Your responsibilities will include developing and maintaining block level test benches, Vplan, regression, and coverage closure, as well as working on test benches with real number modeling. Additionally, you will be involved in netlist and gate level simulations.,