FPGA Prototyping/Emulation Engineer Ceremorphic
Ceremorphic
Office Location
Full Time
Experience: 3 - 3 years required
Pay:
Salary Information not included
Type: Full Time
Location: Hyderabad
Skills: Verilog, System Verilog, RTL, Perl, FPGA, synthesis, timing closure, ASIC design, PCIe, dma, ARM, IP cores, Tcl, AXI protocols
About Ceremorphic
Job Description
The role requires you to take ownership and lead the design, implementation, and verification of FPGA prototypes for next-generation SOCs. Your responsibilities will include FPGA integration of all interfaces such as PCIe, DDR, etc, implementation, and timing closure. Additionally, you will be responsible for providing emulation platform solutions for firmware development and pre-silicon validation, as well as FPGA validation and debugging. Key Requirements: - Utilize Verilog and System Verilog for design, porting large designs to FPGA, and incorporating custom RTL and IP cores. - Experience in FPGA implementation, synthesis (Synplify/Vivado), and timing closure using Vivado. - Ability to partition a large ASIC design into multiple FPGA sub-systems and develop modules for interconnection between these sub-systems. - Proficiency in Perl, Tcl language. - Proficient in hardware debug using FPGA debug tools like Chipscope and lab debug equipment such as Oscilloscopes and Logic Analyzers for identifying and resolving issues at silicon or board level. - Hands-on experience with PCIe controller, DMA, AXI protocols, and ARM. - Collaborate closely with the software team and engage in hardware-software co-debugging.,