Field-Programmable Gate Arrays Engineer ApexPlus Technologies
ApexPlus Technologies
Office Location
Full Time
Experience: 2 - 2 years required
Pay:
Salary Information not included
Type: Full Time
Location: Hyderabad
Skills: VHDL, Verilog, SystemVerilog, PS, PL, EMC, Matlab, C, Python, MicroBlaze, RS232, Vivado, AXI peripherals, Zynq, Xilinx FPGAs, Timing Constraints, external memory, Test Benches, Simulations, bare metal C code, Schematics, State Machines
About ApexPlus Technologies
Job Description
The requirement is immediate so please only apply if you can join immediately or in about 1 month. Please fill this form to take things forward: https://forms.gle/ud4gp7Uq7bRhGhQt5 FPGA Developer Requirements: 1) Should be comfortable with Vivado 2) Coding language: VHDL/Verilog/SystemVerilog 3) Should have developed AXI peripherals for Zynq and other Xilinx FPGAs. Should have a knowledge of the PS and PL parts. 4) Should know how to implement timing and other constraints 5) Should know how to interface external memory using the EMC in Vivado 6) Should know how to write test benches and run simulations 7) Should have a working knowledge of Matlab, C & Python 8) Should know how to configure Microblaze and run bare metal C code 9) Should know how to write PC side code for interfacing over RS232 10) Should know how to read schematics 11) Should have implemented State Machines,