ASIC DV Engineer, Networking Meta
Meta
Office Location
Full Time
Experience: 3 - 3 years required
Pay:
Salary Information not included
Type: Full Time
Location: Karnataka
Skills: Design Verification, IP, Test Planning, UVM, Formal Verification, emulation, Hardware, ASIC, System on Chip SoC, Data Center Applications, Full Stack Software, PostSilicon
About Meta
Job Description
Meta is hiring Application-Specific Integrated Circuit (ASIC) Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design Verification to build IP and System On Chip (SoC) for data center applications. As a Design Verification Engineer, you will be part of a team working with the best in the industry, focused on developing ASIC solutions for Metas data center applications. You will be responsible for the verification closure of a design module or sub-system from test-planning, UVM based testbench development to verification closure. Along with traditional simulation, use other approaches like Formal and Emulation to achieve a bug-free design. The role also provides ample opportunities to partner and collaborate with full stack software, hardware, ASIC Design, Emulation and Post-Silicon teams towards creating a first-pass silicon success.,