Explore Job Openings at Eximietas Design

Employees - 100+, Positions - 35+, Salary - 0 - 0 , Industry Type - IT - Software

Eximietas Design Overview

Welcome to the career portal of Eximietas Design on MYTAT! We're thrilled that you're considering joining our team. Below are the latest job openings available at our company. We are constantly growing, so be sure to check back regularly for new opportunities.

Eximietas Design Current Job Openings

Here are the latest job opportunities available at Eximietas Design:

Firmware Developer

  • Client name Eximietas Design
  • Location Office Location
  • Employment type Full Time
  • General Skills
  • Communication
  • Teamwork

Salary Information not included

Big Data Developer

  • Client name Eximietas Design
  • Location Office Location
  • Employment type Full Time
  • General Skills
  • Communication
  • Teamwork

Salary Information not included

Bluetooth Testing Engineer

  • Client name Eximietas Design
  • Location Office Location
  • Employment type Full Time
  • Python
  • devops
  • Cloud
  • problem-solving

Salary Information not included

WLAN Test Engineer

  • Client name Eximietas Design
  • Location Office Location
  • Employment type Full Time
  • Python
  • devops
  • Cloud
  • problem-solving

Salary Information not included

Full-Stack Application Developer

  • Client name Eximietas Design
  • Location Office Location
  • Employment type Full Time
  • General Skills
  • Communication
  • Teamwork

Salary Information not included

AI-ML Lead Engineer

  • Client name Eximietas Design
  • Location Office Location
  • Employment type Full Time
  • Python
  • devops
  • Cloud
  • problem-solving

Salary Information not included

Senior Android Developer

  • Client name Eximietas Design
  • Location Office Location
  • Employment type Full Time
  • General Skills
  • Communication
  • Teamwork

Salary Information not included

QA Engineer API Automation

  • Client name Eximietas Design
  • Location Office Location
  • Employment type Full Time
  • Python
  • devops
  • Cloud
  • problem-solving

Salary Information not included

Design Verification Engineer

  • Client name Eximietas Design
  • Location Office Location
  • Employment type Full Time
  • Python
  • devops
  • Cloud
  • problem-solving

Salary Information not included

RTL Engineer

  • Client name Eximietas Design
  • Location Office Location
  • Employment type Full Time
  • Python
  • devops
  • Cloud
  • problem-solving

Salary Information not included

SOC Design for Test Engineer

  • Client name Eximietas Design
  • Location Office Location
  • Employment type Full Time
  • Python
  • devops
  • Cloud
  • problem-solving

Salary Information not included

Senior Design Verification Lead (PCIE)

  • Client name Eximietas Design
  • Location Office Location
  • Employment type Full Time
  • PCIe
  • Ethernet
  • MIPI
  • DDR
  • System Verilog
  • assertions
  • Team Management
  • SoC Design Verification
  • Highspeed peripherals
  • Lowspeed peripherals
  • CXL
  • HBM
  • functional coverage
  • Gatelevel simulations
  • Poweraware Verification
  • Synopsys VCS
  • Cadence Xsim
  • Mentorship

Salary Information not included

Verification Team Lead

  • Client name Eximietas Design
  • Location Office Location
  • Employment type Full Time
  • Design Verification
  • GLS
  • ASIC flow
  • SVUVM coding
  • RAL
  • AMBA protocols
  • Low speed peripherals
  • Highspeed protocol
  • Memory protocols
  • Verification tools
  • Revision control flow
  • Power aware simulation
  • Team lead role

Salary Information not included

Analog Circuit Design

  • Client name Eximietas Design
  • Location Office Location
  • Employment type Full Time
  • Serdes
  • IO Design
  • Oscillators
  • PLL
  • Analog Integrated Circuit Design
  • Simulation Tools SPICE
  • DCDC converters

Salary Information not included

ASIC SOC RTL Design Lead (Architect)

  • Client name Eximietas Design
  • Location Office Location
  • Employment type Full Time
  • ASIC SOC RTL Design
  • ARM Processor Integration
  • Design Concepts
  • ASIC flow Understanding
  • SDC Understanding
  • STA reports
  • CDC logic Knowledge
  • AMBA buses
  • Processor Architectures
  • FPGA Experience
  • Tool Experience
  • JTAG Debugging
  • Low Power Design Techniques

Salary Information not included

Senior RTL Lead Microarchitect

  • Client name Eximietas Design
  • Location Office Location
  • Employment type Full Time
  • RTL design
  • Verilog
  • SystemVerilog
  • Logic synthesis
  • Python
  • Perl
  • Microarchitecture development
  • lowpower design techniques
  • Tcl

Salary Information not included

Configuration Manager

  • Client name Eximietas Design
  • Location Office Location
  • Employment type Full Time
  • Configuration management
  • version control
  • change control
  • collaboration
  • Documentation
  • Communication skills
  • Baseline Establishment
  • Baseline Management
  • Auditing
  • Reporting
  • Tool Management
  • Knowledge of CM Tools
  • Change Management Expertise
  • Attention to Detail
  • ProblemSolving Skills
  • Familiarity with DevOps

Salary Information not included

Senior Analog Layout Engineer

  • Client name Eximietas Design
  • Location Office Location
  • Employment type Full Time
  • Electromigration
  • IR drop
  • selfheating
  • RC delay
  • parasitic capacitance optimization
  • Cadence
  • SYNOPSYS
  • scripting languages PERLSKILL

Salary Information not included

RTL Engineer (Microarchitect)

  • Client name Eximietas Design
  • Location Office Location
  • Employment type Full Time
  • RTL design
  • VHDL
  • Verilog
  • System Verilog
  • ARM
  • Networking
  • Performance Analysis
  • Communication
  • Teamwork
  • Formal Verification
  • Python
  • Perl
  • Microprocessor Design
  • Cadence
  • SYNOPSYS
  • Mentor Graphics
  • Optimization techniques
  • Problemsolving
  • lowpower design techniques
  • Validation methodologies

Salary Information not included

DFX Engineer

  • Client name Eximietas Design
  • Location Office Location
  • Employment type Full Time
  • Verilog Coding
  • JTAG
  • SoC RTL verification
  • GLS simulations
  • Test Mode verification
  • Pattern generation
  • Silicon debug

Salary Information not included

Senior Physical Design Lead

  • Client name Eximietas Design
  • Location Office Location
  • Employment type Full Time
  • physical design
  • synthesis
  • RTL
  • static timing analysis
  • Physical verification
  • PR tools
  • VLSI engineering

Salary Information not included

Senior Analog Layout Lead/Architect

  • Client name Eximietas Design
  • Location Office Location
  • Employment type Full Time
  • Electromigration
  • IR drop management
  • selfheating optimization
  • RC delay optimization
  • parasitic capacitance optimization
  • layout effects on circuit
  • Design Constraints
  • Cadence
  • SYNOPSYS
  • lower FINFET technology nodes
  • Scripting skills in PERL
  • Scripting skills in SKILL

Salary Information not included

Senior Physical Design Leads / Architects

  • Client name Eximietas Design
  • Location Office Location
  • Employment type Full Time
  • physical design
  • synthesis
  • RTL
  • static timing analysis
  • Physical verification
  • PR tools
  • VLSI engineering

Salary Information not included

Senior Analog Design Leads

  • Client name Eximietas Design
  • Location Office Location
  • Employment type Full Time
  • analog circuit design
  • Mixed Signal Design
  • Bandgap References
  • DLL
  • DDR
  • Analog Layout
  • Voltage monitors
  • SERDES blocks
  • Transmitter
  • CTLE
  • Sal
  • Phase Interpolator
  • DFE
  • FFE
  • Die to Die interconnect
  • HBM
  • UCIe protocols
  • FINFET Technology Nodes
  • Cadence
  • SYNOPSYS

Salary Information not included

Analog IC Design Lead/Architect

  • Client name Eximietas Design
  • Location Office Location
  • Employment type Full Time
  • CMOS Analog design
  • OTA
  • TIA
  • S2P
  • Samplers
  • Charge Pump
  • Bandgap Reference
  • Ring Oscillator
  • LCVCO
  • SERDES blocks
  • DRV
  • P2S
  • Serializer
  • RCOMP
  • Calibration blocks
  • Receiver Front end
  • CTLE
  • DFE
  • CDR Loop
  • Phase Interpolators
  • Deserializer
  • FFEs
  • Pre drivers
  • Level Shifters
  • V2I circuits
  • Slicers
  • Cadence Virtuoso Schematic
  • Layout editors
  • MOS device operation

Salary Information not included

Senior Analog Circuit Design Engineer

  • Client name Eximietas Design
  • Location Office Location
  • Employment type Full Time
  • CMOS Analog design
  • OTA
  • TIA
  • S2P
  • Samplers
  • Charge Pump
  • Bandgap Reference
  • Ring Oscillator
  • LCVCO
  • SERDES blocks
  • DRV
  • P2S
  • Serializer
  • RCOMP
  • Calibration blocks
  • Receiver Front end
  • CTLE
  • DFE
  • CDR Loop
  • Phase Interpolators
  • Deserializer
  • FFEs
  • Pre drivers
  • Level Shifters
  • V2I circuits
  • Slicers
  • Cadence Virtuoso Schematic
  • Layout editors
  • MOS device operation

Salary Information not included

Analog Circuit Design Engineer

  • Client name Eximietas Design
  • Location Office Location
  • Employment type Full Time
  • CMOS Analog design
  • OTA
  • TIA
  • S2P
  • Samplers
  • Charge Pump
  • Bandgap Reference
  • Ring Oscillator
  • LCVCO
  • SERDES blocks
  • DRV
  • P2S
  • Serializer
  • RCOMP
  • Calibration blocks
  • Receiver Front end
  • CTLE
  • DFE
  • CDR Loop
  • Phase Interpolators
  • Deserializer
  • FFEs
  • Pre drivers
  • Level Shifters
  • V2I circuits
  • Slicers
  • Cadence Virtuoso Schematic
  • Layout editors
  • MOS device operation

Salary Information not included

Firmware Engineer

  • Client name Eximietas Design
  • Location Office Location
  • Employment type Full Time
  • Firmware development
  • Storage Solutions
  • Debugging
  • Troubleshooting
  • C programming
  • SAS
  • SATA
  • PCIe
  • Assembly Programming
  • NVMe

Salary Information not included

Analog Design Engineer

  • Client name Eximietas Design
  • Location Office Location
  • Employment type Full Time
  • Bandgap References
  • DLL
  • DDR
  • Analog Layout
  • Analog mixed signal design
  • Voltage monitors
  • SERDES blocks
  • Transmitter
  • CTLE
  • Sal
  • Phase Interpolator
  • DFE
  • FFE
  • Die to Die interconnect
  • HBM
  • UCIe protocols
  • FINFET Technology Nodes
  • Cadence
  • SYNOPSYS

Salary Information not included

Analog Layout Lead

  • Client name Eximietas Design
  • Location Office Location
  • Employment type Full Time
  • Electromigration
  • IR drop
  • selfheating
  • RC delay
  • parasitic capacitance optimization
  • CADENCESYNOPSYS layout tools
  • scripting languages PERLSKILL

Salary Information not included

Senior Analog Layout Design Lead

  • Client name Eximietas Design
  • Location Office Location
  • Employment type Full Time
  • Electromigration
  • IR drop
  • selfheating
  • RC delay
  • parasitic capacitance optimization
  • Cadence
  • SYNOPSYS
  • scripting languages PERLSKILL

Salary Information not included

Senior Design Verification Architect

  • Client name Eximietas Design
  • Location Office Location
  • Employment type Full Time
  • PCIe
  • SystemVerilog
  • UVM
  • Python
  • Perl
  • AMBA protocols
  • Tcl

Salary Information not included

Sr. Analog Layout Engineer

  • Client name Eximietas Design
  • Location Office Location
  • Employment type Full Time
  • Electromigration
  • scripting languages
  • Perl
  • Communication skills
  • IR drop
  • selfheating
  • RC delay
  • parasitic capacitance optimization
  • Cadence
  • SYNOPSYS
  • SKILL

Salary Information not included

RTL Micro Architect

  • Client name Eximietas Design
  • Location Office Location
  • Employment type Full Time
  • RTL design
  • Verilog
  • System Verilog
  • Logic synthesis
  • Python
  • Perl
  • Microarchitecture design
  • lowpower design techniques
  • Scripting Tcl

Salary Information not included

ASIC SOC RTL Design Lead (Micro-architecture)

  • Client name Eximietas Design
  • Location Office Location
  • Employment type Full Time
  • SDC
  • UPF
  • ASIC SOC RTL Design
  • ARM Processor Integration
  • Design Concepts
  • ASIC flow
  • STA reports
  • CDC logic
  • AMBA buses
  • Processor Architectures
  • FPGA Experience
  • Low Power Design Techniques
  • JTAG Debugging

Salary Information not included